Tzu-Chien Hsueh

Tzu-Chien Hsueh is an Associate Professor in the Department of Electrical and Computer Engineering at the University of California, San Diego. His research focuses on analog and mixed-signal integrated circuits for wireline communication systems, data centers, Ethernet, electrical-optical interfaces, silicon photonics, and high-speed data links. He leads the Integrated Communication Circuits Lab (ICCL) at UC San Diego. Dr. Hsueh's work includes the development of transceivers, serializers-deserializers (SerDes), clock-and-data recovery (CDR), and other circuits for broadband data communications and computations. He has contributed to Intel's high-speed wireline communication projects and has served on various IEEE and Intel technical committees. Dr. Hsueh received his B.S. and M.S. in Electrical Engineering from National Taiwan University and his Ph.D. in Electrical and Computer Engineering from UCLA.

Tzu-Chien Hsueh is a researcher at the University of California, San Diego, focusing on high-speed interconnect technologies and advanced signal processing techniques. His work addresses challenges in on-chip communication, including crosstalk cancellation, power efficiency, and high-speed data transmission. Hsueh's research spans the design of scalable parallel I/O systems, digital clock calibration, and integrated resistors with resistive memory elements. He has contributed to the development of high-speed serial links with advanced equalization techniques and has explored applications in photonic-electronic accelerators for linear algebra operations. His research also includes the analysis of power supply noise and single-photon detection in quantum applications.