Krste Asanović

Krste Asanović is Professor Emeritus and Professor in the Graduate School in the EECS Department at the University of California, Berkeley. His research areas include computer architecture, VLSI design, parallel programming, and operating system design. He leads the RISC-V project at Berkeley and is Chief Architect at RISC-V International. He also co-founded SiFive Inc. to support commercial use of RISC-V processors. Asanović is an Associate Director at the Berkeley Wireless Research Center. His work has been published in numerous conferences and journals, and he has contributed to significant research in computer architecture and system design.

Krste Asanovic is a researcher at UC Berkeley with expertise in Computer Architecture, VLSI Design, and Parallel Programming. His work focuses on developing innovative computing systems and architectures, including parallel computing frameworks, RISC-V instruction set architecture, and hardware design methodologies. He has contributed to the creation of tools like Chisel, Rocket Chip Generator, and Chipyard, which enable efficient hardware design and simulation. His research also explores advanced topics such as silicon-photonic networks, energy-aware data compression, and trusted execution environments. Asanovic's publications highlight his commitment to advancing scalable, efficient, and secure computing technologies.