ZHANG Lining

ZHANG Lining is an Assistant Professor in the School of Electronic and Computer Engineering at Peking University. His research interests include new logic and memory devices, electronic design automation (EDA), and neuromorphic devices and computing systems. He has contributed to the development of advanced CMOS device modeling, novel logic and memory devices, and neuromorphic circuit EDA. His work has been published in IEEE journals and conferences, and he has received awards such as the IEEE EDSSC Best Paper Award and the William Mong Outstanding Paper Award. He is also an IEEE Senior Member and has served on various IEEE technical committees.

Lining ZHANG is a researcher at Peking University with expertise in Compact Modeling, Device Modeling, Semiconductor Device Physics, and DTCO. Their work focuses on the development of compact models for advanced transistors, including double-gate tunnel FETs, cylindrical surrounding-gate MOSFETs, and junctionless nanowire transistors. ZHANG's research also explores novel semiconductor materials such as two-dimensional transition metal dichalcogenides and IGZO for electronics and optoelectronics. Additionally, they investigate device-level solutions for ESD protection and contact fuse technologies in standard CMOS processes. Their contributions span both fundamental device physics and practical circuit simulation tools.