Regular biography
Jason H. Anderson is a Professor in the Electrical & Computer Engineering Department at the University of Toronto. He received his BSc degree in Computer Engineering from the University of Manitoba and his MASc and PhD degrees in Electrical & Computer Engineering from the University of Toronto. Dr. Anderson joined Xilinx, Inc. in 1997, working on computer-aided design tools for integrated circuits. From 2005 to 2008, he managed groups at Xilinx focused on placement, routing, and strategic research and development. He joined the ECE Department at the University of Toronto in 2008 and holds the Jeffrey Skoll Endowed Chair in Software Engineering. His research interests include CAD, architecture, circuits, and applications for field-programmable gate arrays (FPGAs) and coarse-grained reconfigurable arrays (CGRAs). Dr. Anderson serves on the program committees of various international conferences, including the IEEE International Conference on Field-Programmable Technology (FPT), the ACM International Symposium on Field-Programmable Gate Arrays (FPGA), and the International Conference on Field-Programmable Logic and Applications (FPL). He was General Chair of ACM FPGA 2018, Program Chair of ACM FPGA 2017, and Program Co-Chair of FPL 2017. He was also Chief Scientific Advisor and Co-Founder of LegUp Computing Inc., which was acquired by Microchip Corporation in 2020. Dr. Anderson is a Fellow of IEEE and a Member of ACM.
Scholar-generated biography
Jason Anderson is a Professor of Electrical and Computer Engineering at the University of Toronto, specializing in the design and optimization of reconfigurable computing systems. His research focuses on coarse-grained reconfigurable architectures, high-level synthesis, and field-programmable gate arrays (FPGAs), with an emphasis on low-power circuits and secure embedded systems. Anderson's work explores methods for improving FPGA performance, power efficiency, and design automation, including tools like LegUp and VTR. His research also addresses challenges in power reduction, such as clock gating and active leakage power optimization, as well as architectural modeling and mapping for heterogeneous FPGAs.