Jianyi Cheng

Jianyi Cheng is a Lecturer in Computer Architecture at The University of Edinburgh, Department of Computer Science. Their research interests include computer architecture and related areas. Cheng can be contacted via email at jianyi.cheng@ed.ac.uk or through their profile page at https://www.ed.ac.uk/Jianyi_Cheng.html.

Jianyi Cheng is a researcher at the University of Edinburgh with expertise in high-level synthesis, computer architecture, formal methods, machine learning, and hardware security. Their work focuses on advancing high-level synthesis through scalable frameworks, dynamic and static scheduling techniques, and compiler transformations. Cheng's research also explores the integration of machine learning in hardware design, including test stimuli generation and low-rank quantization error reconstruction. Additionally, they investigate memory arbitration, latency optimization, and efficient hardware acceleration for large language models. Their contributions aim to improve the performance, security, and scalability of hardware systems through innovative synthesis and optimization techniques.