Paolo Ienne

Paolo Ienne is a Full Professor at the École Polytechnique Fédérale de Lausanne (EPFL), Department of Computer Science. He heads the Processor Architecture Laboratory (LAP) and has been a professor at EPFL since 2000. Prior to joining EPFL, he worked for the Semiconductors Group of Siemens AG, Munich, Germany, where he was at the head of the Embedded Memories unit in the Design Libraries division. His research interests include computer and processor architecture, FPGAs and reconfigurable computing, electronic design automation, and computer arithmetic. Ienne has received Best Paper Awards at several international conferences and has served in various leadership roles at renowned conferences. He is also an associate editor of several ACM journals.

Paolo Ienne is a professor specializing in reconfigurable computing, electronic design automation, VLSI design methodologies, computer architecture, and computer arithmetic. His research focuses on advancing embedded systems through innovative design techniques, including automatic instruction-set extensions, hardware-software integration, and efficient arithmetic circuit design. He has contributed to the development of customizable embedded processors, dynamic scheduling in high-level synthesis, and power analysis countermeasures. His work also explores FPGA accelerators, on-chip networks, and novel approaches to improve NAND flash lifetime. Ienne's research emphasizes the integration of domain-specific languages and virtualized execution environments to enhance system performance and flexibility.